Firm Overview
Services
Attorneys &
Patent
Professionals
News &
Information
Helpful Links
Career
Opportunities
Contact Us
|
|
Srini Chakravarthi
Phone: (972) 732-1001
Fax: (972) 732-9218
E-mail: chakravarthi@slater-matsil.com
BIOGRAPHY
Srini Chakravarthi has many years of experience in semiconductor R&D, and is internationally recognized for contributions in various areas of semiconductor technology. At the firm, Srini focuses on patent prosecution over a range of advanced technologies. Srini enjoys working with inventors in developing and protecting the full potential of their ideas.
Srini brings a unique expertise that spans various areas of engineering and science (nanotechnology, materials, and electrical). Srini's background includes more than six years of technology development at Texas Instruments' flagship research and development division. As a result, Srini developed a broad knowledge base and invaluable experience in various fields of engineering. Due to his technical expertise, he also served in a patent review panel to evaluate patenting new ideas. Srini was also a key innovator, and is a named inventor in at least 14 issued patents.
As an engineer, Srini worked in device design and technology computer aided design, and developed state of the art technologies at 90 nm and 45 nm. Consequently, he is intimately familiar with silicon technology development: from technology definition to product yield. For example, he was amongst the early teams demonstrating embedded SiGe stressors, now commonly used in silicon technology. Srini played a critical role in the development and yield of local strained silicon technologies. Both these works, for example, were showcased at VLSI symposiums, the leading platform for presenting semiconductor technology.
His strong technical background coupled with his curiosity of physics enabled Srini to develop an in-depth knowledge of a number of technologies. For example, he has modeled and explained phenomena that span various spatial, dimensional and temporal ranges: from nanotechnology to electrical devices. Consequently, Srini's expertise also extends to software engineering especially to semiconductor software tools.
EDUCATION
Srini's graduate education was at the cross-roads of electrical engineering and materials science, and included fundamental modeling of nano scale mechanisms observed during semiconductor fabrication. For this original work, Srini obtained a doctorate in engineering from Boston University in 2000. He received his bachelor's engineering degree from India's prestigious engineering school: Institute of Technology, Banaras Hindu University (1995).
Srini is currently enrolled in Southern Methodist University's evening law program.
TECHNICAL RECOGNITION
Srini is internationally recognized amongst his peers for his contributions in the area of silicon technology, and this recognition includes:
- Member TI Patent Review Committee: 2005-2007;
- Symposium session chair at international meeting of Materials Research Society in 2007;
- Technical Program Committee of one of the oldest international modeling conference (SISPAD) 2006; and
- Refereed submissions for a number of scholarly scientific journals including Journal of Applied Physics, Applied Physics Letter, Journal of Vacuum Science and Technology, Microelectronics Reliability, Electron Device Letters, and Transactions of Electron Devices.
AWARDS
- Outstanding paper award at International Reliability Physics Symposium 2004, which is amongst the most prestigious awards in the international reliability community;
- Elected (2005) to TI's exclusive Technical Ladder in recognition of technical contributions to TI (Member Group of Technical Staff);
- Member of Technical Staff, TI: 2001-2005;
- Graduate research assistant, Boston University: doctoral research funded by Semiconductor Research Corporation under Prof. Scott Dunham, now at Dept. of Electrical Engineering, University of Washington; and
- Amongst the top 2% in the Indian Engineering Entrance Exam (IIT-JEE), 1990, perhaps the toughest engineering entrance worldwide.
SPEECHES & PUBLICATIONS
Srini has presented a number of talks, including many invited presentations, in leading international conferences. Srini has authored more than 50 publications in leading journals and conferences. For example, his work has appeared in peer reviewed scholarly publications such as Journal of Applied Physics, Applied Physics Letters, Journal of Physics, Transactions of Electron Devices, Electron Device Letters, Microelectronic Reliability; as well as prestigious conferences such as International Electron Device Meeting, VLSI-Devices, International Reliability Physics Symposium, Simulation of Semiconductor Processes and Devices, Materials Research Society Meetings, and Electrochemical Society Meetings. A selected few articles and presentations include:
- "Probing negative bias temperature instability using a continuum numerical framework: physics to real world operation," S. Chakravarthi, Microelectronics Reliability, 47, 863-872, Elsevier Science (2007), and International Workshop on Computational Electronics (IWCE-11), Vienna, (2005), (Invited);
- "Atomistic based process modeling for state of the art nanoscale CMOS device design," S. Chakravarthi, NanoTech 2003, Nano Science and Technology Institute, (Invited);
- "Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing," P.R. Chidambaram, C. Bowen, S. Chakravarthi, C. Machala, and R. Wise, Special Issue on Non-Classical Si CMOS Devices and Technologies: Extending the Roadmap, IEEE Trans. Elec. Dev., 53, 944- 964, (2006), (Invited Review Paper);
- "Design of CMOS transistors to maximize circuit FOM using a coupled process and mixed-mode simulation methodology," R. Venugopal, S. Chakravarthi, and P.R. Chidambaram, Electron Device Letters, 27, 863 - 865, (2006); and
- "A simple continuum model for boron clustering based on atomistic calculations," S. Chakravarthi and S.T. Dunham, Journal of Applied Physics, 89, 3650-3655, (2001) (American Institute of Physics).
PATENTS
With many critical inventions, Srini is a named inventor on several awarded patents. For example, some of his patents (7,112,516, 7,129,127) were recently highlighted by US Fed News, federal patent awards. Srini's awarded patents include:
- 6,682,980: Fabrication of abrupt ultra-shallow junctions using angled PAI and fluorine implant;
- 6,797,593: Methods and apparatus for improved mosfet drain extension activation;
- 6,830,980: Semiconductor device fabrication methods for inhibiting carbon out-diffusion in wafers having carbon-containing regions;
- 6,847,089: Gate edge diode leakage reduction;
- 6,849,528: Fabrication of ultra shallow junctions from a solid source with fluorine implantation;
- 6,852,603: Fabrication of abrupt ultra-shallow junctions;
- 6,927,137: Forming a retrograde well in a transistor to enhance performance of the transistor;
- 7,033,879: Semiconductor device having optimized shallow junction geometries and method for fabrication thereof;
- 7,061,058: Forming a retrograde well in a transistor to enhance performance of the transistor;
- 7,112,516: Fabrication of abrupt ultra-shallow junctions;
- 7,118,977: System and method for improved dopant profiles in CMOS transistor;
- 7129,127: Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation;
- 7,179,696: Phosphorus activated NMOS using SiC process; and
- 7,208,380: Interface improvement by stress application during oxide growth through use of backside films.
|
u